1. Field of the Invention
This invention relates to a semiconductor device and a manufacturing method thereof and more particularly to a semiconductor device having MISFETs that are designed to improve the performance and reliability and a manufacturing method thereof.
2. Description of the Related Art
Recently, much attention is paid to the technique for enhancing the mobility of carriers (electrons) in the channels of pMOSFETs that are one type of MISFETs. As one example thereof, source and drain portions of pMOSFETs are first recessed in the technique described in Jpn. Pat. Appln. KOKAI Publication No. 2006-186240. Then, a silicon-germanium (SiGe) film is filled in the recessed regions by use of a selective epitaxial growth technique. Next, stress from the SiGe film is applied to the recessed regions to give compressive stresses to the channels of the pMOSFETs and cause strain in Si. Thus, the mobility of carriers (charges) in the channels of the pMOSFETs is enhanced.
The above technique is called an eSiGe technique, for example. However, if the above structure and manufacturing method are used, the following problems (1) to (4) tend to occur in the MOSFET manufacturing process.
(1) Problem Related to Film Formation of SiGe Film:
In order to form a high-quality SiGe film, it is necessary to sufficiently remove oxygen and carbon adhered to the surfaces of recessed regions in the preprocess step. In order to attain this, it is desirable to subject the surfaces of the recessed regions to a hydrofluoric acid process by a sufficiently large etching amount. However, since the gate sidewalls are generally formed of silicon dioxide (SiO2) and also etched in the hydrofluoric acid process, an amount to be etched is limited. Further, if the gate sidewalls are generally formed of SiO2 films by use of an LP-CVD method, the etching rate thereof becomes several times higher than that of an SiO2 film formed by thermal oxidation. Therefore, for example, if the gate sidewall is formed of a CVD-SiO2 film having an etching rate which is five times that of a thermal oxide film and the gate sidewall is formed to a thickness of approximately 20 nm, the gate sidewall will be eliminated when an SiGe film with a film thickness of as small as approximately 4 nm is etched. As a result, SiGe films will be formed on the side surfaces of the gate electrode. Thus, it is difficult to adequately perform a preprocess step for the SiGe film.
(2) Problem Related to Filling of Offset Sidewall:
In order to solve the problem (1), for example, it is only required to form the gate sidewalls by use of silicon nitride (SiN) films. However, if the gate sidewalls are formed of SiN films, an SiGe film tends to be formed into a shape in which it rises from the surface of the silicon substrate to cover the surfaces of the gate sidewalls like the shape formed by use of the normal epitaxial growth method. That is, if the gate sidewalls are formed of SiN films, the surface of the SiGe film that faces the gate sidewall is formed into a reversed taper form in which it is inclined and set closer to the gate sidewall as it is separated away from the surface of the silicon substrate. In the SiGe film having no so-called facet, offset sidewalls are formed not only on the sidewall portions of the gate electrode but also on the sidewalls of the SiGe film that faces the gate electrode in an offset sidewall formation step that is a later step.
For example, it is supposed that the relation of L<2OSW is set between the distance L from the side surface of the gate electrode that faces the SiGe film to the junction portion between the SiGe film and an extension diffusion layer and the thickness OSW of the offset sidewall. In this case, an extension diffusion layer formation region of the silicon substrate surface that is exposed between the gate electrode and the SiGe film will be filled with an offset sidewall material in the offset sidewall formation step. Further, even if the relation of L>2OSW is set between L and 2OSW, an offset sidewall will be formed on the sidewall of the SiGe film that faces the gate electrode as described before. Therefore, a region used to from an extension diffusion layer is markedly reduced. As a result, the parasitic resistance of a MOSFET is increased and the performance thereof is lowered.
(3) Problem Related to Lowering in Reliability of Gate Oxide Film in Gate Edge:
In the step of removing the gate sidewalls, edge portions of the gate oxide film are exposed and etched. Therefore, the reliability of the edge portion of the gate oxide film and the reliability of the MOSFET are degraded.
(4) Problem Related to Entry of Silicide into Channel Portion:
In the general eSiGe technique, an SiGe film is formed into such a shape that it gets into under a gate sidewall formed in a later step. If a nickel silicide (NiSi) film is formed on the SiGe film with the above shape, there occurs a possibility that the NiSi film will be formed into the internal portion of the extension diffusion layer region below the gate sidewall. Therefore, the reliability of the MOSFET may be degraded and a junction leak may occur in the extension diffusion layer region.